Sequential storage circuits that store data in response to a clock signal in data processing circuits are known. These circuits include latch circuits and flip flops and are very important elements of a processing circuit from both a delay and energy standpoint. Flip flops can take the form of master slave latches which input the data to the master latch during the first phase of the clock cycle and transfer it to the slave latch during the second phase of the clock cycle. This makes them look as though they store data in response to an edge, in other words they appear edge triggered, although in effect the latches are transparent in response to one phase of the clock cycle and opaque in response to the other, so the storage element can receive the data during one phase and then be isolated from the input during the other.
These devices are used to store operational or functional data during processing and they are also often used to store diagnostic data. In such cases they often operate in one of two modes, these being diagnostic mode and operational mode. Such a flip flop traditionally has a scan input and a data input. The scan input receiving diagnostic data and the operational input receiving operational data. The mode of operation is controlled by a scan enable signal, the diagnostic mode being entered when the scan enable signal is high and in this mode diagnostic data is received, stored and output. When the scan enable signal is low operational data is received, stored and output instead.
FIG. 1 shows how a signal travelling between a flip flop 10 termed the source flip flop and a further flip flop 20 termed the destination flip flop follows either an operational data path where it passes through combinational circuitry 25 where data processing operations occurs or along a diagnostic data path where it is transmitted directly to the destination flip flop 20. Thus, depending on the mode of operation either a data value D or a diagnostic data value SI are selected by the source flip flop for transmission in response to a clock signal CLK.
If diagnostic mode of operation is selected then the scan enable SE signal is high and multiplexer 12 selects the data output from the source flip flop 10 to follow the diagnostic data path 13 directly to the destination flip flop 20. As this data path has no combinational logic on it then if the clock signals are not perfectly aligned and the destination clock has a slight delay with respect to the source clock, then if the clock at the destination flip flop 20 goes high making the master latch within the flip flop transparent and allowing data at the input to be received, before the clock at the source flip flop 10 goes high and becomes opaque, then the old data value will be captured rather than the new data value. This is shown by the illegal arrow on the timing diagram. This is called a hold timing violation and occurs on the scan or diagnostic data path owing to the lack of elements on this path that allows data to be transmitted very quickly. The hold time is the amount of time the data should be held steady after the clock event to ensure that it is reliably sampled.
This problem has been addressed in devices of the prior art by providing inverters on the diagnostic data paths that buffer the signal and introduce a time delay. A drawback with this is that as the number of sequential elements in a circuit increases then so too do the number of buffers required to buffer this value and this can lead to significant effects on the area of the resulting circuit. Given that these buffers are only there to enable the scan path to function correctly this is a large overhead for a relatively unimportant function.
A further way of addressing this problem has been to insert a lock up latch between the two latches of the flip flop which introduces a delay. A drawback of this is that it is an external separate clocked element and the clocks need balancing.